1. Field of the Invention
The present invention relates to a solid-state image sensor used for video cameras, digital cameras, cell phones with built-in cameras, and the like, and a fabrication method thereof. More specifically, the present invention relates to a solid-state image sensor such as a MOS-type image sensor of a threshold voltage modulation type and a fabrication method thereof.
2. Description of the Related Art
Conventionally, CCD type image sensors, MOS type image sensors, and the like are known as solid-state image sensors for converting image light as an image signal into an electric signal. For example, MOS-type image sensors include light-receiving areas for generating electric charges by light irradiation (photodiode) and transistors for reading out the electric charges generated in the light-receiving areas as an electric signal (MOS transistor), which are both provided on a shared substrate. Such MOS-type image sensors consume less power compared to CCD-type image sensors. Moreover, they can utilize standard CMOS process techniques such as system LSIs. Thus, the MOS-type image sensors have the advantages that the cost can be reduced, and they can be generally used.
Recently, as ion implantation apparatuses have been developed, as disclosed in Japanese Laid-Open Publication No. 2002-26303, for forming impurity regions in light receiving areas of solid-state image sensors, maximum concentration portions in the substrate depth direction can be formed at desired positions. Thus, it is possible to control the concentration efficiently.
Japanese Laid-Open Publication No. 2001-223351 discloses MOS-type image sensors of a threshold voltage modulation type. The MOS-type image sensors of the threshold voltage modulation type can be fabricated by using the techniques described in Japanese Laid-Open Publication No. 2002-26303.
In the image sensors of the threshold voltage modulation type disclosed in Japanese Laid-Open Publication No. 2001-223351, MOS transistors and photodiodes are provided on the same substrate. Below gate electrodes of the MOS transistors, electric charge storage areas called hole pockets are provided. The electric charge storage areas have embedded structure so that electric charges generated in the light-receiving areas are stored for suppressing implantation of photo-generated electric charges to surface defectives of semiconductor layers in order to reduce noises. In photodiodes which are the light-receiving areas, the electric charges generated by light irradiation (holes) are stored in the electric charge storage areas. The threshold voltages of the MOS transistors are modulated in proportion to the amount of the stored electric charges. Accordingly, the MOS-type image sensors of the threshold voltage modulation type can read out a signal in accordance with the amounts of the electric charges stored in the electric storage areas. Thus, noises due to electric charges other than photo-generated electric charges and dark current can be maintained low.
The MOS-type image sensors of the threshold voltage modulation type disclosed in Japanese Laid-Open Publication No. 2001-223351 will be described with reference to FIGS. 6 and 7.
FIGS. 6A and 6B are schematic cross-sectional views for respectively illustrating a fabrication process for fabricating the MOS-type image sensors of the threshold voltage modulation type. In a MOS-type image sensor, a light-receiving receiving diode (photo diode) 60 and a MOS transistor 100 are provided on the same substrate. Hereinafter, only the main portions of the light-receiving receiving diode 60 and the MOS transistor 100 will be explained.
As shown in FIG. 6A, the conventional MOS-type image sensor of the threshold voltage modulation type includes a silicon substrate 50 including a p-type epitaxial semiconductor layer (hereinafter, referred to as a silicon substrate 50), and an n-type impurity region 58 corresponding to the photo diode 60 and a p-type impurity region 57 adjacent to the n-type impurity region 58, which are formed on the silicon substrate 50.
On the silicon substrate 50, an n-type layer 59 is laminated so as to cover the p-type impurity region 57 and the n-type impurity region 58. On the n-type layer 59, a p-type impurity region 54 and an n-type low-concentration impurity region 53 are laminated in this order in an area corresponding to the p-type impurity region 57 and the n-type impurity region 58. The laminated p-type impurity region 54 and the n-type low-concentration impurity region 53 are surrounded by n-type well separation regions 56 formed on the n-type layer 59.
In the silicon substrate 50 with the impurity regions formed therein, a gate insulation film 51 is formed so as to cover an entire surface of the silicon substrate 50. Then, on the gate insulation film 51, a gate electrode 52 of a ring shape in the MOS transistor 100 is formed at the position adjacent to the n-type well separation regions 56 in the area above the p-type impurity region 54. On a surface of the n-type low-concentration impurity region 53, the gate insulation film 51 remains as a remainder from a dry etching process for the gate electrode 52.
Next, as shown in FIG. 6B, by implanting ions with having the gate electrode 52 as a mask and the gate insulation film 51 as an implantation protection film, n-type impurity regions 55 to be a source region and a drain region of the MOS transistor 100 are formed. At this time, in the area of the light-receiving receiving diode 60, embedded structure for photo-generated electric charges are formed by forming the n-type impurity regions 55 on an upper surface of the p-type impurity region 54. The n-type impurity regions 55 have high concentrations, and are formed at a shallow position with respect to the surface of the silicon substrate 50. By forming the high-concentration n-type impurity regions 55 in the area of the light-receiving receiving diode 60 at the shallow position with respect to the surface of the silicon substrate 50, short-wavelength blue light which may be attenuated radically near the surface of the silicon substrate 50 can be received securely with a high intensity without attenuation of the strength.
FIG. 7 shows n-type impurity concentration distribution in the depth length from the surface of the silicon substrate 50 for the light receiving diode 60 fabricated as described above. The vertical axis in FIG. 7 indicates the impurity concentration. The horizontal axis in FIG. 7 indicates the distance (depth) from the surface of the silicon substrate 50.
As shown in FIG. 7, the n-type impurity regions 55 is formed to the position at the depth around 200 nm (0.2 μm) from the surface of the silicon substrate 50. The peak of the impurity concentration of the n-type impurity regions 55 is at the depth of 50 nm or less from the surface of the substrate.
In the conventional MOS transistor 100 of the threshold voltage modulation type, the impurity concentration region is formed to be shallow (thin) with respect to the surface of the light receiving diode 60 in order to securely receive the blue light which has a short wavelength and is radically attenuated near the surface at a high intensity without attenuating the intensity.
However, when a dry etching process for the gate electrode 52 is performed, the gate insulation film 51 remains on the surface of the silicon substrate 50, and there is a variance in the film thickness of the remaining gate insulation film 51. Thus, when the n-type impurity regions 55 of a surface portion of the light receiving diode 60 are formed by ion implantation, a variance may be generated in peak positions of the impurity concentration of the n-type impurity regions 55 due to the variance in the film thickness of the gate insulation film 51, which serves as an implantation protection film. A variance may also be generated in the embedding resistance with respect to the photo-generated electric charges in the light receiving diode 60.
Further, the gate insulation film 51 remains after the dry etching with the film thickness of about 300 angstrom. For forming n-type impurity regions 55 on the surface of the light receiving diode 60, it is necessary to perform ion implantation at a low energy. However, when there is gate insulation film 51 of about 300 angstrom, the distance from a surface of the gate insulation film 51 and the surface of the silicon substrate 50 becomes long. This cause problems that a variance in an ion implantation range when ions are implanted (ARp) becomes large and an extent of the impurity region in the depth length of the silicon substrate 50 becomes large.
Further, if an average range when ion implantation impurities are implanted is set to a position deep inside from the surface of the silicon substrate 50, implantation defects may be generated in the light receiving diode 60 and a surface leak current may be undesirably generated.
Moreover, when the gate electrode 52 is formed by using a plasma process, if plasma gives damage on an upper-most surface of the light receiving diode 60, a surface leak current due to surface defects may be undesirably generated.